As is known, the most commonly used method of reading memory cells is to compare a quantity related to the current flowing through the memory cell to be read with a similar quantity related to the current flowing through a reference cell of known content, and using a circuit arrangement of the type shown in FIG. 1.
Number 1 in FIG. 1 indicates a circuit for reading the cells of a memory array, comprising an array branch 2 connected by an array bit line 5 to an array cell 4 to be read; and a reference branch 3 connected by a reference bit line 9 to a reference cell 8 of known content.
Array branch 2 comprises a current-voltage converter 6--hereinafter referred to as an array converter--connected on one side to array bit line 5 by a decoding circuit (not shown), and on the other side to a supply line 7 at voltage V.sub.cc.
Reference branch 3 comprises a current/voltage converter 10--hereinafter referred to as a reference converter--connected on one side to reference bit line 9 by a decoding circuit (not shown), and on the other side to supply line 7.
Each current/voltage converter 6 and 10, respectively, comprises a precharge and biasing circuit 11 and 12 (for appropriately biasing the respective bit lines 5 and 9 to prevent spurious write phenomena, such as soft-writing, and possibly also for equalizing lines 5 and 9) and a respective load 13 and 14 connected in series with each other. The nodes 15 and 16 between respective precharge and biasing circuits 11 and 12 and respective loads 13 and 14 form the outputs of respective current/voltage converters 6 and 10 and are connected to the input of a sense amplifier 17 for comparing the voltages of nodes 15 and 16 to determine the content of array cell 4.
Load 13 comprises a P-channel MOS transistor with a predetermined channel width to length ratio W.sub.1 /L.sub.1. Load 14 comprises a diode-connected P-channel MOS transistor with a channel width to length ratio W.sub.2 /L.sub.2 that is N times greater than ratio W.sub.1 /L.sub.1, and MOS transistors 13 and 14 present the control terminals connected to each other, the source terminals connected to supply line 7, and the drain terminals connected respectively to nodes 15 and 16 to form a current mirror in which the current flowing in transistor 13 is N times less than that flowing in transistor 14.
Array bit line 5 is connected to a number of array cells 4 located in the same array column, and the capacitances of which are shown schematically in FIG. 1 by an equivalent array capacitor 18, which, for the sake of simplicity, is shown connected directly to node 15. Similarly, reference bit line 9 is connected to a number of reference cells located in the same reference column, and the capacitances of which are shown schematically in FIG. 1 by an equivalent reference capacitor 19 connected to node 16.
To safely determine the content of array cell 4, i.e., whether the cell is erased or written, reference cell 8, when biased at a given read voltage, generates a reference current I.sub.R, the value of which is mirrored in array branch 6 and is between the value of the current generated by an erased array cell 4 and the value of the current generated by a written array cell 4. In the FIG. 1 circuit, therefore, sense amplifier 17 compares the value of the voltage V.sub.R present at reference node 16 and related to current I.sub.R generated by reference cell 8, with the value of the voltage V.sub.M present at array node 15 and related to the difference between the current I.sub.M generated by array cell 4 and the current I.sub.O supplied by load 13 (and in turn equal to the current IR mirrored--multiplied by factor 1/N--in array branch 2).
To give a clearer idea of the concept involved, the FIG. 2 diagram shows the characteristics I.sub.DS .dbd.f(V.sub.GS) of array and reference cells 4 and 8. More specifically, A indicates the characteristic of array cell 4 when erased (distributed about that of reference cell 8); B indicates the characteristic of array cell 4 when written, C indicates the characteristic of reference cell 8 as mirrored by mirror circuit 13 and 14 in array branch 2; V.sub.th1 is the threshold value of the erased array cell 4; and V.sub.th2 is threshold value of the written array cell 4. As can be seen, in the FIG. 1 circuit solution, the slope of mirrored characteristic C of reference cell 8 is less by a factor N than that of characteristics A and B of erased and written array cells 4, due to the current I.sub.O flowing in transistor 13 being N times less than that imposed by reference cell 8 in transistor 14, and the characteristic of reference cell 8 presents a reference threshold value equal to the threshold value V.sub.th1 of erased array cell 4.
As shown in FIG. 2, in the FIG. 1 circuit solution, the maximum read voltage of array and reference cells 4 and 8 is substantially equal to the value at which characteristic B of written array cell 4 intersects characteristic C of reference cell 8, and, since the read voltage also represents the supply voltage of read circuit 1, there is therefore a limit to the maximum permissible supply voltage value V.sub.cc.
To overcome the problem, according to a (not shown) solution described in EP-A-O 676 768 published on Nov. 10, 1995, the characteristic of reference cell 8 is approximated, not by a single straight line, but by a broken line comprising two segments: a first segment presenting the same slope as curve C in FIG. 2 and comprised between the threshold voltage of an erased cell and a predetermined intermediate voltage; and a second segment presenting the same slope as curves A and B. By being divided into two segments, the characteristic of reference cell 8 (shown by the dotted-line curve D in FIG. 2) lies between characteristics A and B and no longer intersects characteristic B of written array cell 4, even in the event of a high read, and hence supply, voltage.
In the known solutions described, the ratio between the current flowing in loads 13 and 14 is essential, as stated, for distinguishing the written from the erased cells. In fact, as is known, to reduce the read time of array cells 4 when erased, the current flowing in array cell 4 must be much greater than that flowing in transistor 13 so as to rapidly discharge capacitor 18 and hence rapidly reduce the voltage at node 15. Whereas, to reduce the read time of array cells 4 when written, the current generated by reference cell 8 must be high, so that the corresponding mirrored current I.sub.O in transistor 13 rapidly charges capacitor 18 and so brings the voltage at node 15 rapidly to a value close to that of supply voltage Vcc.
The present tendency, however, is to reduce supply voltage as far as possible to permit wider use of read circuits 1, even in portable equipment and low-supply applications. Reducing the supply voltage, however, results in a considerable reduction in the currents I.sub.R, I.sub.M generated by array and reference cells 4, 8 and hence an increase in the read time of circuit 1.